1. Field of the Invention
Embodiments relate to the field of device manufacturing. More particularly, the present invention relates to a method, system and structure for performing implantation in a CMOS device.
2. Discussion of Related Art
As semiconductor devices such as CMOS devices scale to smaller dimensions, the ability to extract enhanced performance increasingly depends on integration of new device structures, materials, and processes. One recent innovation involves the use of embedded material to enhance device performance, such as an embedded SiGe (eSiGe) material, which may especially enhance PFET (P type field effect transistor) performance, and embedded Si:C (eSi:C), which may enhance NFET (N type field effect transistor) performance.
The formation of embedded structures entails etching portions of a source/drain (S/D) region to form a cavity, and refilling the cavity with a desired material, such as eSiGe, which may improve device properties by straining the crystalline lattice of field effect transistor (FET) and thereby improving majority carrier mobility.
FIGS. 1a-1d depict a prior art process for forming an eSiGe device. In the process depicted, cavities between gates are filled with e-SiGe material having “sigma shaped” sides, which allows for proximity between the eSiGe stressor and a neighboring gate. This technique has been developed for both 45 and 32 nm technology nodes for CMOS devices.
As illustrated at FIG. 1a, a substrate 10 includes multiple gates 12. The gates may act as masks for an etch process that etches the material of the substrate 10, which may be silicon. As depicted in FIG. 1b, the surface of the substrate 10 is etched between gates 12 to form a set of cavities 14 having steep sidewalls, which is typically formed by a dry etch process. Subsequently, as depicted at FIG. 1c, a wet etch is performed, which selectively etches certain crystallographic planes of the material of the substrate 10 faster than others, resulting in a “sigma shape” cavity 15. Typical etchants used for the wet etch process are potassium hydroxide (KOH) or tetramethyl ammonium hydroxide (TMAH). Subsequently, as depicted at FIG. 1d, embedded material 16, which may be a SiGe or Si:C material, is regrown in the cavities 15.
The embedded material 16 may induce a stress in the channel regions under gates 12, thereby improving performance, as noted. However, the formation of cavities 15 may encroach upon the extension regions 18 that lie underneath gate sidewalls 20. Because of the nature of the wet etch process, material of the substrate 10 may be removed from extension regions 18 during formation of cavities 14, which may undesirably affect device properties after the cavities are filled with embedded material 16.
In order to prevent or retard wet etching of the extension regions 18 during cavity 15 formation, it may be desirable to protect the extension regions 18 before subjecting the cavities 14 to a wet etch. For example, the etch rate of silicon substrates in KOH/TMAH may be lower when the silicon is amorphized. Accordingly, amorphization of extension regions may be desirable.
FIGS. 2a and 2b depict one conventional approach for pre-amporphizing a substrate 10 before cavity formation. As illustrated in FIG. 2a, ions 22 bombard the substrate 10, forming amorphous regions 26 between gates 24 that overlap extension regions 18. In a subsequent step, a sidewall material 28, which may be an insulator such as silicon nitride, is deposited by a known method, such as low pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD) However, after deposition of sidewall material 28 by LPCVD or ALD, the thermal budget that is typically required to form the sidewalls may be sufficient to recrystallize the amorphous regions 26, as depicted in FIG. 2b. After recrystallization, the substrate 10 retains its original single crystal structure including in the extension regions 18, rendering them susceptible to etch during formation of sigma shaped cavities. It will be appreciated, therefore, that improvements are desirable in present day methods for producing cavity structures in substrates.